Test Daily Abbreviations

Bin N 比例上升 / 下降 / 飆 / 平穩。Bin trend 是 PQA 看 yield 的第一張圖。

• Bin 7 climbed 3% week-over-week — likely Vt drift.
• Bin 6 dropped after the probe card cleaning — contact issue resolved.

單 bin / 雙 bin 上限被超過 / 通過 / 接近 / 觸及。SBL breach 通常代表 lot reject。

• SBL for Bin 8 was breached at 0.7% — lot held for re-test.
• DBL on Bins 6+7 is clear — lot released.

探針卡被清潔 / 更換 / 重新對位 / 修整。Probe card 是測試耗材,接觸電阻飆就要動。

• Probe card was cleaned every 2,000 touchdowns to keep contact resistance stable.
• Probe card replaced after needle wear exceeded 20 microns.

重測救回 N% 的 fail die。Retest pass 率高通常代表 contact 問題不是真的 die fail。

• Retest recovers 30% of Bin 6 fails — contact issue confirmed.
• Retest cleared 0% — these are real fails, not retest-able.

測試時間縮短 / 拉長 / 浪費。Tester time 是測試成本主要驅動,每秒幾毛美金。

• Tester time was shortened by 15% after the program optimization.
• Tester time wasted on retests is adding up — clean the probe card.

Wafer map 顯示某種圖樣。Edge ring、center cluster、streak 都有特定根因。

• Wafer map shows edge ring fail — likely chamber edge issue.
• Wafer map reveals streak pattern — probe card touchdown alignment issue.

PCM 量測偏移 / 在 / 跑出 spec。PCM 跑出 spec 通常先於 yield drop 出現。

• PCM Rs shifted +5% above target — process drift indicator.
• PCM Vt fell out of spec on lot 1842 — implant root cause.

測試良率下降 / 維持 / 復原。CP yield 是 wafer 品質的最後一道評分。

• Test yield fell off from 92% to 87% on lot Q3-218 — investigating.
• Test yield holds steady at 91% for three consecutive lots — recovery confirmed.

bin pareto

Bin pareto on lot lot_id: top fail bin is bin at N%; second is bin2 at M%.

{批號} 的 Bin Pareto:第一 fail bin 是 {bin} 占 {N}%;第二是 {bin2} 占 {M}%。Yield review 必出現。

• Bin pareto on lot Q3-218: top fail bin is Bin 7 at 2.4%; second is Bin 6 at 1.1%.▸ 聽念法
• Bin pareto on lot 1842: top fail bin is Bin 9 at 1.8%; second is Bin 11 at 0.6%.▸ 聽念法

SBL excursion

Lot lot_id breached SBL on bin: actual% vs limit limit%; recommend action.

{批號} 違反 SBL 在 {bin}:實際 {actual}% vs 上限 {limit}%;建議 {動作}。

• Lot Q3-218 breached SBL on Bin 8: 0.7% vs limit 0.5%; recommend hold and 100% retest.▸ 聽念法
• Lot 1842 breached SBL on Bin 6: 1.2% vs limit 1.0%; recommend probe card replacement and retest.▸ 聽念法

wafer map analysis

Wafer map on lot_id shows pattern; likely root cause is module; recommend investigation.

{批號} 的 wafer map 顯示 {pattern};根因可能在 {模組};建議 {調查}。

• Wafer map on lot Q3-218 shows edge ring fail; likely root cause is etch chamber edge; recommend chamber correlation analysis.▸ 聽念法
• Wafer map on lot 1842 shows center cluster fail; likely root cause is CMP dishing on wide pads; recommend post-CMP defect inspection.▸ 聽念法

retest disposition

Retest on scope recovered N%; remaining fails attributed to category; lot disposition: action.

{範圍} 重測救回 {N}%;剩餘 fail 歸屬 {類別};lot 處置:{動作}。

• Retest on lot Q3-218 Bin 6 fails recovered 30%; remaining fails attributed to true device fails; lot disposition: ship per SBL after re-binning.▸ 聽念法
• Retest on lot 1842 Bin 8 fails recovered 5%; remaining fails attributed to true Vt out-of-spec; lot disposition: hold pending FA.▸ 聽念法

tester economics

Tester time on product: N ms/die; cost cost/die; optimization target target.

{產品} 的測試時間:{N} ms/顆;成本 {cost}/顆;優化目標 {target}。

• Tester time on Product X: 220 ms/die; cost $0.35/die; optimization target 180 ms/die.▸ 聽念法
• Tester time on Product Y: 80 ms/die; cost $0.12/die; optimization target 60 ms/die.▸ 聽念法

Email — Bin 7 Spike Investigation

Test 部門早會發給 PQA + PIE,Bin 7 突然飆。

Subject: [INVESTIGATING] Bin 7 spike on Product X — last 4 lots

Hi all,

Quick update on the Bin 7 trend that PQA flagged this morning.

Symptom: Bin 7 (Vt out of spec) on Product X climbed from baseline 0.8% to 2.4% over the last four lots (Q3-217 through Q3-220).

Initial cross-reference:
- All 4 lots ran the source/drain extension implant on implanter Y between 03/09 and 03/12.
- Bin 7 spike pattern on the wafer map is uniform across wafer — points to dose-related issue, not chamber-edge.
- Implant team confirmed dose monitor drift on implanter Y (15% under-dose).

Containment:
- 4 affected lots held at WAT.
- Bin 7 limit (SBL = 2.0%) breached on lot Q3-220. Hold disposition pending implant root cause confirmation.
- Implant team running re-cal monitor wafers tonight.

Will share confirmation by tomorrow EOD.

Thanks,
Test ENG

相關縮寫:Bin · SBL · WAT · Vt

Conf Call — Weekly Test Yield Review

週度 yield review,Test lead 帶 90 秒 wrap-up。

Thanks. Quick wrap on this week's test yield.

CP yield came in at 88.6%, 2.4% below the 91% running average. Three trends drove the gap:

First — Bin 7 spike on Product X (Vt out of spec): 2.4% vs 0.8% baseline. Root cause confirmed by implant team: dose drift on implanter Y. Filament replaced; monitor wafers re-cal'd dose to target. Recovery confirmed on last two lots.

Second — Bin 6 (open contact) on Product Y: 1.5% vs 0.9% baseline. Wafer map shows streak pattern correlating with probe card touchdown count. Probe card cleaning interval tightened from 2,500 to 2,000 touchdowns. New schedule in effect.

Third — small contributor: Bin 11 (leakage) on Product Z trending up slowly, 0.4% vs 0.2%. PCM data shows gate oxide thickness drifting +0.3 nm. Will track at thin film side.

FT yield held at 98.2% — no excursions on the final test side.

SBL events this week: one — Product X lot Q3-220 breached Bin 7 limit. Held; awaiting implant root cause sign-off.

PCM data: M2 Rs trending +3% — PIE is aware, tracking.

Action items:
- Probe card touchdown count tightening — close ECN by Friday.
- Implant filament confirmation lot tonight.

Open to questions.

相關縮寫:CP · FT · Bin · SBL · PCM · PIE

Deviation Report — SBL Breach on Bin 8

Test 部門寫的 SBL 違規 deviation report Section 4 + 5。

4.0 Root Cause Analysis — SBL Breach on Bin 8

4.1 Symptom
Lot Q3-241 breached SBL on Bin 8 (leakage too high): measured 0.7%, limit 0.5%. Lot held immediately post-CP test.

4.2 Investigation Path
- Wafer map: failures clustered at wafer edge, ring pattern from edge to ~10 mm inward.
- Probe card inspection: clean; touchdown count well within service interval.
- PCM cross-reference: gate oxide Rs at wafer edge shows +8% from center — confirms physical leak path, not contact issue.
- TEG extraction confirms gate oxide thinning at the edge (3.2 nm vs 3.5 nm target).

4.3 Root Cause Statement
The Bin 8 leakage excursion is attributed to gate oxide thinning at the wafer edge on the M0 RTA chamber A, with non-uniform thermal coupling at edge regions. Confirmed by PCM mapping, TEG extraction, and chamber correlation.

5.0 Containment & Long-Term Action

5.1 Containment
- Lot Q3-241 held at CP; pending PQA disposition.
- All wafers from M0 RTA chamber A in past week reviewed; 3 additional lots flagged for enhanced screening.
- RTA chamber A pulled for thermal re-cal.

5.2 Long-Term
- Edge-zone temperature monitor added to RTA SPC chart.
- Quartz window inspection moved to monthly cadence from quarterly.
- FMEA updated to include "edge thermal non-uniformity → gate oxide thinning → Bin 8 leakage" as a critical failure path.

相關縮寫:SBL · CP · PCM · TEG · RTA · SPC · FMEA

讀完了?來測驗看看記住了沒。